High density integrated circuitry is principally fabricated from semiconductor wafers. An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers. Upon fabrication completion, a wafer contains a plurality of identical discrete die areas which are ultimately cut from the wafer to form individual chips. Die areas or cut dies are tested for operability, with good dies being assembled into separate encapsulating packages which are used in end-products or systems.
CMOS is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of produced holes or electrons.
NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functionally dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS represented a lower-power technology capable of exploiting large scale integration fabrication techniques.
Fabrication of semiconductor circuitry includes numerous processing steps in which certain areas of a semiconductor substrate are masked while other areas are subjected to processing conditions such as various etching steps and doping steps. In an effort to optimize semiconductor processing, efforts in the industry have been focused on reducing the number of processing steps in any particular processing flow. Reducing the number of processing steps required in a particular processing flow saves valuable processing time and subjects the wafer to less risk of destruction.
In typical CMOS processing, separate photomasking processing steps are utilized to both open up contact openings to conductive lines formed over the substrate, as well as to expose substrate active areas into which dopants or conductivity changing impurity were to be added. Such separate processing of course adds to processing time and effort. It is desirable to reduce the number of required processing steps associated with forming integrated circuitry. It is also desirable to improve upon current semiconductor processing techniques.
This invention arose out of concerns associated with reducing the number of processing steps required to produce integrated circuitry in particular CMOS circuitry. This invention also grew out of concerns associated with improving formation of PMOS active area diffusion regions associated with CMOS circuitry.